Show HN: E80: an 8-bit CPU in structural VHDL
Recorded: Jan. 20, 2026, 10:03 a.m.
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Stokpan/E80
mainBranchesTagsGo to fileCodeOpen more actions menuFolders and filesNameNameLast commit messageLast commit dateLatest commit History8 CommitsAssemblerAssembler GHDLGHDL GowinGowin InstallerInstaller ModelSimModelSim QElectroTechQElectroTech QuartusQuartus VHDLVHDL VivadoVivado .gitattributes.gitattributes .gitignore.gitignore LICENSELICENSE README.mdREADME.md View all filesRepository files navigationREADMEGPL-3.0 licenseE80 CPU Low floor, as it depends purely on textbook-based, structural VHDL components, and offers a toolchain installer for one-click simulation. This makes it easy to use, capable of running pretty complex and realistic programs, and can be used in multiple lab or classroom scenarios. Feature Dependencies Execution Word Size Buses Instruction size RAM Register file Registers Stack Architecture Addressing Input Output Assembly syntax Assembler Simulated on Editor Synthesized on Tested on ISA cheatsheet +----------+----------+-------+---------------+-----------------------+-------+ Notes ROR R1,R2 rotates R1 to the right by R2 bits. This is equivalent to left rotation by 8-R2 bits. Flags cheatsheet Assembly cheatsheet +----------------------+----------------------------------------------------+ +----------------------+----------------------------------------------------+ Notes Directives must precede all instructions. Example 1 - One-click simulation with GHDL/GTKWave or ModelSim To simulate it, first install the E80 Toolchain package from the Releases, then open the E80 Editor and paste the code into it: Notice that syntax highlighting for the E80 assembly language has been enabled by default for all code (except for VHDL files). Notice that the HLT instruction has stopped the simulation in GHDL, allowing for the waveforms to be drawn for the runtime only. This useful feature is supported in ModelSim as well. Notice how the assembler formats the output into columns according to instruction size, and annotates each line to its respective disassembled instruction, ASCII character or number. The Memory Data tab next to the Wave tab contains the RAM in the end of simulation. The contents can also be displayed by hovering on the RAM in the Wave tab, but there's a catch: if the radix is set to ASCII and the data include a curly bracket, ModelSim will throw an error when trying to show the tooltip. The top module (FPGA.vhd) uses three 8-LED rows for display, and the joystick buttons for control: Row A (Status): [7:4] (Flags): Carry, Zero, Sign, Overflow. Row B (Data): Displays the value of the selected register. When Reset is held, it mirrors the DIP switch input instead. Buttons Joystick Left/Right: Adjust clock speed; supports auto-repeat when held down. To run the test, paste the following program into the editor and press F7. This will automatically update Firmware.vhd with your new code. You can also simulate (F5 or F8) the program prior to running in the FPGA; in this case it's suggested to match the .SIMDIP value with the DIP switches on the board. About A simple CPU in VHDL for educational purposes cpu assembly vhdl gcc assembler isa microworld modelsim ghdl digital-design cyclone-iv quartus gowin tang-primer-25k Resources Readme GPL-3.0 license Uh oh! There was an error while loading. Please reload this page. Activity 12 1 0 Report repository Releases E80 Toolchain Setup 1.6 Latest Packages No packages published Languages C VHDL NSIS Stata Lua Batchfile Tcl Footer © 2026 GitHub, Inc. Footer navigation Terms Privacy Security Status Community Docs Contact Manage cookies Do not share my personal information You can’t perform that action at this time. |
The E80 CPU, developed by Stokpan as part of an undergraduate thesis, is a simplified central processing unit implemented in VHDL, designed explicitly for educational purposes. It embodies the principles of a Constructionist Microworld by offering three key characteristics: a low floor for accessibility, a high ceiling for complexity, and wide walls for compatibility across platforms. The CPU’s design prioritizes textbook-based structural VHDL components, ensuring that it remains grounded in foundational digital logic principles while providing a toolchain installer for one-click simulation. This makes it an accessible resource for students learning about computer architecture, as it balances simplicity with functionality. The E80 supports a comprehensive set of instructions typical of Computer Architecture textbooks, including stack operations and subroutine calls, while its compatibility with various platforms—such as GHDL/GTKWave, ModelSim, Quartus Lite, Gowin Education, Vivado Standard, and the Tang Primer 25K FPGA board—enhances its utility in diverse lab or classroom environments. The repository includes all necessary source materials, from the CFG grammar defining its assembly syntax to EDA project files, enabling users to study, modify, and extend the design. The CPU’s architecture is load/store based, with a register-register model, allowing for efficient data manipulation. Its 8-bit word size and 16-bit instruction format accommodate variable-length instructions (either one or two words), while its buses—8-bit data, 8-bit address, and 16-bit instruction—reflect a balanced approach to memory addressing and data transfer. The CPU features a multiport register file (1R/W, 1R, 1W) with six general-purpose registers (R0–R5), a flags register (R6), and a stack pointer (SP, alias R7). The stack is implemented as full descending, initialized to 0xFF on reset, allowing for standard subroutine calls and stack-based operations. Input is handled via an 8-bit memory-mapped DIP switch at address 0xFF, while output includes flags, register values, the program counter (PC), and a clock signal displayed through three 8-bit LEDs. The assembly syntax combines elements of ARM, x86, and textbook pseudocode, offering a hybrid approach that bridges high-level programming concepts with low-level hardware control. For instance, instructions like `MOV R3,R5` translate to binary representations such as 0b(00011000 00110101), which corresponds to the hexadecimal value 0x1835. This syntax is further supported by an ISO C99 assembler, which processes user-written programs into machine code executable within the simulated or synthesized environment. The ISA includes a range of operations, from basic arithmetic and logic (ADD, SUB, AND, OR, XOR) to more complex instructions like ROR (rotate right), LSHIFT (left shift), and RSHIFT (right shift). Conditional jumps (e.g., JC, JZ, JS) allow for branching based on the state of flags, while stack operations (PUSH, POP) and subroutine calls (CALL, RETURN) enable modular programming. The CPU’s flag system—comprising Carry (C), Zero (Z), Sign (S), Overflow (V), and Halt (H)—is updated by arithmetic, logic, and shift instructions, with specific rules for determining their values. For example, the Carry flag is set during addition if the result exceeds 8 bits, while the Overflow flag indicates signed arithmetic overflows. The HLT instruction halts execution by setting the H flag, freezing the program counter (PC) and stopping further processing. The repository also provides detailed documentation on the CPU’s behavior, including a flags cheatsheet that clarifies how signed and unsigned operations affect flag states. For instance, during addition (ADD), the Carry flag reflects whether the result exceeds 255 (unsigned overflow), while the Overflow flag indicates if the sum falls outside the range of -128 to 127 (signed overflow). Similarly, subtraction (SUB) and comparison (CMP) instructions update flags based on the relationship between operands. The E80’s assembly language includes directives like `.TITLE`, `.LABEL`, `.SIMDIP`, and `.DATA` to manage program structure, memory allocation, and simulation parameters. These directives allow users to define labels for addresses, set DIP switch inputs for simulations, and embed data directly into memory. The assembler also supports comments (using semicolons) and flexible operand formats, such as immediate values, register addresses, and memory references (e.g., `[R2]` for the value at address stored in register R2). The repository’s examples demonstrate practical applications of the CPU, such as a program that converts lowercase characters in a null-terminated string to uppercase. This example leverages instructions like `LOAD`, `CMP`, `SUB`, and `STORE` to process each character, using conditional jumps (JNC, JC) to determine whether a transformation is needed. Another example tests joystick control on the Tang Primer 25K FPGA, using `ROR` instructions to rotate a value across 256 iterations. The E80’s toolchain simplifies simulation and synthesis, with one-click scripts for GHDL/GTKWave and ModelSim, as well as project files for Quartus Lite, Gowin Education, and Vivado Standard. The repository also includes a SciTE-based editor with syntax highlighting and one-click run functionality, streamlining the development process. For hardware testing, the Tang Primer 25K setup requires pin assignments defined in the `Gowin\E80.cst` file, with specific connections for input (DIP switches) and output (LEDs). The FPGA’s top module (`FPGA.vhd`) uses three rows of LEDs to display flags, register values, and the PC, while a joystick controls clock speed, reset, and register selection. The CPU’s compatibility with multiple platforms ensures that students can experiment with different EDA tools and hardware, reinforcing their understanding of digital design principles. Overall, the E80 CPU serves as a comprehensive educational tool, bridging theoretical concepts with hands-on implementation. Its structured design, detailed documentation, and support for both simulation and physical hardware make it an invaluable resource for learning about computer architecture, VHDL programming, and FPGA development. By combining simplicity with robust features, the E80 empowers learners to explore the inner workings of a CPU while engaging with real-world design challenges. |