GitHub - Essenceia/CRC_generator: CRC Generator is a command-line application that generates Verilog or VHDL code for CRC of any data width between 1 and 1024 and polynomial width between 1 and 1024. The code is written in C and is cross-platform compatible. Written by Evgeni Stavinov. · GitHub

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Essenceia/CRC_generator

 mainBranchesTagsGo to fileCodeOpen more actions menuFolders and filesNameNameLast commit messageLast commit dateLatest commit History10 Commits10 Commitsdocdoc  .gitignore.gitignore  LICENSE.mdLICENSE.md  README.mdREADME.md  crc_gen.cppcrc_gen.cpp  View all filesRepository files navigationREADMEMIT licenseCRC Generator for Verilog or VHDL
Description
CRC Generator is a command-line application that generates Verilog or VHDL code for CRC of any data width between 1 and 1024 and polynomial width between 1 and 1024. The code is written in C and is cross-platform compatible.
Build
To build on linux using gcc:
g++ -o crc_gen crc_gen.cpp
Usage
Invoke the tool via command line:
./crc_gen [language] [data_width] [poly_width] [poly_string]
Options:

language: verilog or vhdl

data_width: data bus width ${1..1024}$

poly_width: polynomial width ${1..1024}$

poly_string: a string that describes CRC polynomial, eg: Ethernet MAC FCS uses poly 04C11DB7

Notes on poly_string
Examples:
$05 = x^5+x^2+1$
$8005 = x^{16} + x^{15}+ x^2+ 1$
The string representation (0x05, 0x8005) doesn’t include highest degree coefficient in polynomial representation ($x^5$ and $x^{16}$ in the above examples).
Output Examples
Printing usage:
./crc_gen

usage:
crc-gen language data_width poly_width poly_string

parameters:
language : verilog or vhdl
data_width : data bus width {1..1024}
poly_width : polynomial width {1..1024}
poly_string : polynomial string in hex

example: usb crc5 = x^5+x^2+1
crc-gen verilog 8 5 05

Generation in action:
./crc_gen verilog 2 4 3

//-----------------------------------------------------------------------------
// Copyright (C) 2009 OutputLogic.com
// This source file may be used and distributed without restriction
// provided that this copyright statement is not removed from the file
// and that any derivative work contains the original copyright notice
// and the associated disclaimer.
// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
//-----------------------------------------------------------------------------
// CRC module for
// data[1:0]
// crc[3:0]=1+x^1+x^4;
//
module crc(
input [1:0] data_in,
input crc_en,
output [3:0] crc_out,
input rst,
input clk);

reg [3:0] lfsr_q,
lfsr_c;
assign crc_out = lfsr_q;
always @(*) begin
lfsr_c[0] = lfsr_q[2] ^ data_in[0];
lfsr_c[1] = lfsr_q[2] ^ lfsr_q[3] ^ data_in[0] ^ data_in[1];
lfsr_c[2] = lfsr_q[0] ^ lfsr_q[3] ^ data_in[1];
lfsr_c[3] = lfsr_q[1];

end // always

always @(posedge clk, posedge rst) begin
if(rst) begin
lfsr_q <= {4{1'b1}};
end
else begin
lfsr_q <= crc_en ? lfsr_c : lfsr_q;
end
end // always
endmodule // crc

Archived version
This repository is a mirror of the version currently found on source forge, duplicated here in an effort to no help preserve this tool into the future.
I, Julia Desmazes, have not contributed in any way to the development of this tool, all credit belongs to the original author.
In addition to being a command line tool, this tool also used to be available interactively though the now defuncts OutputLogic website.

About the original author
Evgeni Stavinov is the creator and main developer of OutputLogic.com. Evgeni has more than 20 years of diverse design experience in the areas of FPGA logic design, embedded software and communication protocols. He holds MSEE from University of Southern California and BSEE from Technion – Israel Institute of Technology. For more information contact evgeni@outputlogic.com
License
This code is licensed under MIT license, all rights reserved to Evgeni Stavinov. See LICENSE for more details.

About

CRC Generator is a command-line application that generates Verilog or VHDL code for CRC of any data width between 1 and 1024 and polynomial width between 1 and 1024. The code is written in C and is cross-platform compatible. Written by Evgeni Stavinov.

Topics

vhdl

verilog

crc

ethernet

galois-field

lfsr

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MIT license

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The CRC Generator is a cross-platform, command-line application developed by Evgeni Stavinov that functions to generate hardware description code, specifically Verilog or VHDL, for Cyclic Redundancy Check (CRC) calculations. The application is implemented in C, which provides the underlying mechanism for generating the necessary specifications for digital logic design. The utility of the tool lies in its capacity to generate code for CRC operations across a wide range of data and polynomial widths, supporting data widths and polynomial widths ranging between 1 and 1024.

The process of generating the code is initiated through command-line invocation. Users specify the desired programming language, the data bus width, the polynomial width, and the polynomial representation string. The application handles the complexity of mapping these mathematical and structural parameters into synthesizable hardware descriptions. For instance, the application allows inputting polynomial information using string representations, such as those found in standards like Ethernet MAC FCS, which relate to generating the specific logic required for the CRC calculation. This capability bridges the gap between abstract mathematical concepts of error control coding and concrete digital circuit implementation.

The core functionality is exemplified by the generation of modules, such as the provided Verilog code snippet, which details the logic necessary for a CRC module. This module demonstrates the internal state logic, including the linear feedback shift register (LFSR) management, which is fundamental to CRC algorithms. The structure involves defining input data, control signals, and the resulting CRC output based on the specified polynomial and data sequence. The logic involves sequential and combinational assignments to manage the state of the register, demonstrating how these abstract generation parameters translate directly into clocked digital logic that can be implemented in hardware.

Evgeni Stavinov, the creator of this tool, brings significant expertise to the development, possessing over twenty years of experience in diverse fields including FPGA logic design, embedded software, and communication protocols. This background informs the tool's focus on generating hardware-relevant descriptions, emphasizing the practical application of digital design principles to error detection. The tool is designed to be used by specifying parameters comprehensively, ensuring that the resulting Verilog or VHDL code accurately reflects the required CRC computation structure for the specified data and polynomial sizes.