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Cache Aware Scheduling Shows Nice Wins for AMD Zen 5 on PostgreSQL, Valkey

Recorded: May 29, 2026, 10 a.m.

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Cache Aware Scheduling Shows Nice Wins For AMD Zen 5 On PostgreSQL, Valkey, Network Performance - Phoronix

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Cache Aware Scheduling Shows Nice Wins For AMD Zen 5 On PostgreSQL, Valkey, Network Performance
Written by Michael Larabel in Software on 27 May 2026 at 10:00 AM EDT. Page 1 of 4. 6 Comments.

The long-in-development work on Cache Aware Scheduling looks like it will come to a head soon with it looking like Cache Aware Scheduling will land for Linux 7.2. Ahead of the upcoming merge window I ran some fresh benchmarks looking at different areas where this feature is shining.

It's been a few months since last trying Cache Aware Scheduling on AMD EPYC Turin as well as Intel Xeon 6 to great success. This round of benchmarking was on an AMD Ryzen Threadripper 9980X within the System76 Thelio Workstation.

Cache Aware Scheduling can help improve Linux performance on modern CPUs with multiple cache domains, such as AMD's modern processors from Ryzen to EPYC. The scheduler tries to help ensure that tasks sharing data are colocated to the same last level cache (LLC) domain for ensuring better cache locality and reducing cache misses/bouncing.
The System76 Thelio Major was equipped with the AMD Ryzen Threadripper 9980X, 4 x 32GB DDR5 memory, 1TB NVMe SSD, and Radeon AI PRO R9700 graphics. Ubuntu 26.04 was running on this workstation for this round of benchmarks while building a custom kernel with the latest patches atop a Linux 7.1-rc2 base.
Cache Aware Scheduling was tested on/off with its runtime controls using the latest patches tentatively slated for Linux 7.2.
Let's look at some of the latest wins out of Cache Aware Scheduling on Linux.

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The work on Cache Aware Scheduling is nearing completion, with expectations that it will be integrated into Linux 7.2. This feature is designed to enhance the performance of Linux systems running on modern Central Processing Units that feature multiple cache domains, such as those found in AMD processors ranging from Ryzen to EPYC. The fundamental goal of Cache Aware Scheduling is to optimize task placement by ensuring that tasks sharing related data are allocated to the same last level cache last level cache domain (LLC). This operational strategy aims to improve cache locality within the system, thereby minimizing cache misses and reducing the performance penalty associated with cache bouncing.

These architectural optimizations are particularly relevant for contemporary multi-core and multi-cache designs. As demonstrated in recent benchmarking efforts, implementing Cache Aware Scheduling yields notable performance advantages when running specific workloads on these advanced CPUs. The testing was conducted using an AMD Ryzen Threadripper 9980X processor within a System76 Thelio Workstation environment. The benchmark setup utilized Ubuntu 26.04 and a custom kernel built upon a Linux 7.1-rc2 base.

The results from these evaluations highlighted significant performance gains in areas relevant to database operations and networking. Specifically, the scheduling feature demonstrated favorable outcomes in benchmarks focusing on PostgreSQL, Valkey, and overall network performance. These findings suggest that the scheduler effectively leverages the nuanced cache structure of modern CPUs to achieve superior resource utilization and reduced latency for data-intensive applications. The research, documented by Michael Larabel, points toward the practical benefits of fine-grained cache awareness in influencing overall system throughput for demanding software environments.