Accurate Models of AMD Matrix Cores
Recorded: Sept. 17, 2026, 12:28 a.m.
| Original | Summarized |
[2609.14845] Accurate Models of AMD Matrix Cores
Skip to main content Search Log in Search arXiv Press Enter to search · Advanced search Computer Science > Hardware Architecture arXiv:2609.14845 (cs) [Submitted on 13 Sep 2026 (v1), last revised 15 Sep 2026 (this version, v2)] Abstract:Matrix multipliers available on recent GPUs do not conform with the IEEE 754 floating point standard. Features of matrix multipliers differ across vendors and architectures of the same vendor, such as accumulator width, rounding behaviour, normalisation points, intermediate underflow and overflow logic, the handling of subnormals, and the treatment of special inputs. As a result, reproducibility of small matrix multiplier results across devices is not possible and cannot be achieved by software control. Implementation details of matrix multipliers are not documented, making it difficult to interpret discrepancies in the computed results. We characterise the numerical behaviour of matrix multipliers across three AMD GPU architectures: CDNA 1, CDNA 2, and CDNA 3, using the MI100, MI210/250, and MI300A/300X GPUs, respectively. We design test vectors to target numerical features for all supported input formats and provide the derivation and the reasoning for why each vector allows to determine a particular numerical feature based on the outputs of the devices. MATLAB-based software models of the matrix multipliers are then developed for each architecture and validated for bit-level reproducibility against hardware using a randomized test suite consisting of 10 million sets of random input vectors. To achieve this, we applied a previously developed technique to iteratively refine the accuracy of the models in a loop, by randomized testing followed by test-refinement until the model matches the hardware for every test case. Finally, as a proof of concept for what experimental research can be done with the models, we have utilised them in two demonstrative numerical applications, quantifying application-level accuracy differences between AMD matrix cores and the NVIDIA tensor cores. Subjects: Hardware Architecture (cs.AR); Mathematical Software (cs.MS) Cite as: Focus to learn more arXiv-issued DOI via DataCite Submission history From: Faizan Ahmad Khattak [view email] [v1]
Full-text links: View a PDF of the paper titled Accurate Models of AMD Matrix Cores, by Faizan A Khattak and Mantas Mikaitis and Carlo J. GrazianiView PDFHTML (experimental)TeX Source view license < prev | new Change to browse by: References & Citations NASA ADSGoogle Scholar export BibTeX citation BibTeX formatted citation loading... Data provided by: Bookmark
Bibliographic Tools Bibliographic and Citation Tools Bibliographic Explorer Toggle Bibliographic Explorer (What is the Explorer?) Connected Papers Toggle Connected Papers (What is Connected Papers?) Litmaps Toggle Litmaps (What is Litmaps?) scite.ai Toggle scite Smart Citations (What are Smart Citations?) Code, Data, Media Code, Data and Media Associated with this Article alphaXiv Toggle alphaXiv (What is alphaXiv?) Links to Code Toggle CatalyzeX Code Finder for Papers (What is CatalyzeX?) DagsHub Toggle DagsHub (What is DagsHub?) GotitPub Toggle Gotit.pub (What is GotitPub?) Huggingface Toggle Hugging Face (What is Huggingface?) ScienceCast Toggle ScienceCast (What is ScienceCast?) Demos Demos Replicate Toggle Replicate (What is Replicate?) Spaces Toggle Hugging Face Spaces (What is Spaces?) Spaces Toggle TXYZ.AI (What is TXYZ.AI?) Related Papers Recommenders and Search Tools Link to Influence Flower Influence Flower (What are Influence Flowers?) Core recommender toggle CORE Recommender (What is CORE?) Author About arXivLabs arXivLabs: experimental projects with community collaborators Which authors of this paper are endorsers? | We gratefully acknowledge support from About Major funding support from |
The authors investigated the numerical behavior of matrix multipliers implemented on various AMD GPU architectures, noting that these multipliers do not adhere to the IEEE 754 floating-point standard. Discrepancies in behavior arise due to differences between vendors and architectures concerning implementation details such as accumulator width, rounding behavior, normalization points, handling of intermediate underflow and overflow, subnormal treatment, and special input management. Consequently, achieving reproducible results for small matrix multiplier operations across different devices is not feasible through software control, further complicated by the undocumented implementation details. To address this lack of knowledge, the researchers characterized these numerical behaviors across three AMD GPU architectures—CDNA 1, CDNA 2, and CDNA 3—by utilizing specific hardware, including the MI100, MI210/250, and MI300A/300X GPUs. The study involved designing specific test vectors aimed at probing these numerical features for all supported input formats, deriving the reasoning for how each vector allows for the determination of specific numerical characteristics based on the device outputs. Subsequently, the authors developed MATLAB-based software models for each architecture. These models were rigorously validated against the actual hardware to ensure bit-level reproducibility, achieved through a method involving randomized testing followed by iterative test-refinement until the model matched the hardware outputs for every test case, using a large set of ten million random input vectors. Finally, the developed models were leveraged as a proof of concept by applying them to demonstrative numerical applications to quantify the differences in application-level accuracy observed between the AMD matrix cores and those found in NVIDIA tensor cores. |