TSMC revealing details about next gen A14 node
Recorded: Sept. 17, 2026, 7:08 p.m.
| Original | Summarized |
IEEE IEDM 2026 | 3-2 | A14 CMOS NanoFlexTM Pro Platform Technology with 2nd Gen. Nano-sheet and Full Node PPA Benefits for HPC/AI and Mobile SoC Applications IEEE IEDM 2026 DOWNLOAD Dec. 12- 16 Menu See more links My Agenda My Profile Recommendations Sign Out Home Attendee Info Registration Details Hotel Fraud Awareness About San Francisco Call for Papers Overview Topics of Interest Paper Preparation Student Info Pre-Publish Restrictions Late News Submission Details Speaker Info Resource Center Preparing Presentation Program Program Overview sessionsearch Session List Schedule at a Glance Expo Become an Exhibitor Exhibitor Resources About About IEDM Organizing Committees IEEE & EDS Information Contacts Best Student Paper Award Press Press Details Press Kit Session Type sessiongallery Floor Plan Login/Agenda See more links My Agenda My Profile Recommendations Sign Out 3-2 | A14 CMOS NanoFlexTM Pro Platform Technology with 2nd Gen. Nano-sheet and Full Node PPA Benefits for HPC/AI and Mobile SoC Applications Level Regular Submission Type Technical Session Abstract A14 NanoFlexTM Pro platform technology features the world’s smallest SRAM with a cell size <0.017μm2 and highest SRAM macro density to date through dimensional ground rule scaling. Coupled with standard cell innovations, it delivers a full-node PPA improvement over the predecessor N2 technology for a 10~15% speed enhancement, a 25~30% power reduction and a chip density increase by ~20% driven by logic and SRAM scaling. Key features, such as TSV, innovative RDL that enables SoIC bond pitch of 4.5μm and high-performance MiM processes, have also been developed to accelerate the system-level integration and scaling for SoIC products. Supported by robust yield and device progress, A14 technology is on track for volume production in 2028. Description Speakers Presenting Author Shien-Yang Wu Taiwan Semiconductor Manufacturing Company (TSMC) Tracks Advanced Logic Technology (ALT) Parent Sessions Mon. Dec. 14 | 1:45 PM IEEE IEDM 2026•©2026 All Rights Reserved Sitemap |
The A14 NanoFlexTM Pro platform technology is introduced, which incorporates a second generation of nano-sheet and full node advancements to deliver significant Power, Performance, and Area (PPA) benefits tailored for High Performance Computing (HPC), Artificial Intelligence (AI), and Mobile System-on-Chip (SoC) applications. This technology features the world's smallest SRAM with a cell size smaller than 0.017 square micrometers, achieving the highest SRAM macro density to date through extensive dimensional ground rule scaling. Coupled with innovations in standard cell design, the A14 technology provides a full-node PPA improvement over the preceding N2 technology, manifesting as a ten to fifteen percent speed enhancement, a twenty-five to thirty percent power reduction, and an approximate twenty percent increase in chip density, all driven by the scaling of logic and SRAM elements. Furthermore, to expedite system-level integration and scaling for SoIC products, the technology includes key features such as Through-Silicon Vias (TSV), innovative Read-Before-Layer (RDL) capabilities that allow for a System-on-Insulator (SoIC) bond pitch of 4.5 micrometers, and high-performance Multi-Mission (MiM) processes. Supported by robust yield and device progress, the A14 technology is projected to enter volume production by 2028. This work was presented by Shien-Yang Wu of the Taiwan Semiconductor Manufacturing Company. |